Mechanism for remapping post virtual machine memory pages

ABSTRACT

According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

COPYRIGHT NOTICE

[0001] Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.

FIELD OF THE INVENTION

[0002] This invention relates to virtual machines of a computer processor such as a microprocessor. In particular, the invention relates to memory management for virtual machines.

BACKGROUND

[0003] An Operating System (OS) is a software program that controls physical computer hardware (e.g., a processor, memory, and disk and CD-ROM drives) and presents application programs with a unified set of abstract services (e.g., a file system). A Virtual Machine Manager (VMM) is also a software program that controls physical computer hardware such as, for example, the processor, memory, and disk drives. Unlike an OS, a VMM presents programs executing within a Virtual Machine (VM) with the illusion that they are executing on real physical computer hardware that includes, for example, a processor, memory and a disk drive.

[0004] Each VM typically functions as a self-contained entity, such that software executing in a VM executes as if it were running alone on a “bare” machine instead of within a virtual machine that shares a processor and other physical hardware with other VMs. It is the VMM that emulates certain functions of a “bare” machine so that software executing within a VM executes as if it were the sole entity executing on the computer.

[0005] Various techniques have been developed to assign physical system memory to virtual machines running on a system. One such technique is the use of partitioned memory. Partitioned memory is where physical system memory is divided into a number of contiguous regions. While partitioned memory is less expensive to implement in the CPU, memory cannot be easily reconfigured dynamically between virtual machines.

[0006] Also various techniques have been developed to obtain greater performance from a given memory capacity. One such technique is the use of virtual memory. Virtual memory is based on the concept that, when running a program, the entire program need not be loaded into main memory at one time. Instead, the computer's operating system loads sections of the program into main memory from a secondary storage device (e.g., a hard disk drive) as needed for execution.

[0007] To make this scheme viable, the operating system maintains tables, which keep track of where each section of the program resides in main memory and secondary storage. As a result of executing a program in this way, the program's logical addresses no longer correspond to physical addresses in main memory. To handle this situation a central processing unit (CPU) maps the program's effective or virtual addresses into their corresponding physical addresses.

[0008] However, in computer systems implementing the partitioned memory technique, it is often desirable to dynamically reallocate memory for each virtual machine. It is also desirable manage memory on an individual page basis, rather than in large regions. With current partitioned memory systems, it is not possible to dynamically reallocate memory. Current partitioned memory systems also impose many limitations on the page level flexibility that many operating systems require to support virtual memory.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.

[0010]FIG. 1 is a block diagram of one embodiment of a computer system;

[0011]FIG. 2 is a block diagram of one embodiment of a processor coupled to a chipset and memory device;

[0012]FIG. 3 is a block diagram for one embodiment of a chipset remapping mechanism;

[0013]FIG. 4 is a flow diagram of one embodiment of converting a virtual address to a page address; and

[0014]FIG. 5 is a block diagram of one embodiment of a bus master coupled to a chipset and memory device.

DETAILED DESCRIPTION

[0015] A mechanism for remapping partitioned virtual machine memory to page granular memory is described. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

[0016] In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

[0017]FIG. 1 is a block diagram of one embodiment of a computer system 100. The computer system 100 includes a processor 101 that processes data signals. Processor 101 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or other processor device.

[0018] In one embodiment, processor 101 is a processor in the Pentium® family of processors including the Pentium® IV family and mobile Pentium® and Pentium® IV processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other processors may be used. FIG. 1 shows an example of a computer system 100 employing a single processor computer. However, one of ordinary skill in the art will appreciate that computer system 100 may be implemented using multiple processors.

[0019] Processor 101 is coupled to a processor bus 110. Processor bus 110 transmits data signals between processor 101 and other components in computer system 100. Computer system 100 also includes a memory 113. In one embodiment, memory 113 is a dynamic random access memory (DRAM) device. However, in other embodiments, memory 113 may be a static random access memory (SRAM) device, or other memory device.

[0020] Memory 113 may store instructions and code represented by data signals that may be executed by processor 101. According to one embodiment, a cache memory 102 resides within processor 101 and stores data signals that are also stored in memory 113. Cache 102 speeds up memory accesses by processor 101 by taking advantage of its locality of access. In another embodiment, cache 102 resides external to processor 101.

[0021] Computer system 100 further comprises a chipset 111 coupled to processor bus 110 and memory 113. Chipset 111 directs data signals between processor 101, memory 113, and other components in computer system 100 and bridges the data signals between processor bus 110, memory 113, and a first input/output (I/O) bus 120.

[0022] In one embodiment, I/O bus 120 may be a single bus or a combination of multiple buses. In a further embodiment, I/O bus 120 may be a Peripheral Component Interconnect adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland, Oreg. In another embodiment, I/O bus 120 may be a Personal Computer Memory Card International Association (PCMCIA) bus developed by the PCMCIA of San Jose, Calif. Alternatively, other busses may be used to implement I/O bus. I/O bus 120 provides communication links between components in computer system 100.

[0023] A network controller 121 is coupled I/O bus 120. Network controller 121 links computer system 100 to a network of computers (not shown in FIG. 1) and supports communication among the machines. In one embodiment, computer system 100 receives streaming video data from a computer 110 via network controller 121.

[0024] A display device controller 122 is also coupled to I/O bus 120. Display device controller 122 allows coupling of a display device to computer system 100, and acts as an interface between the display device and computer system 100. In one embodiment, display device controller 122 is a monochrome display adapter (MDA) card.

[0025] In other embodiments, display device controller 122 may be a color graphics adapter (CGA) card, an enhanced graphics adapter (EGA) card, an extended graphics array (XGA) card or other display device controller. The display device may be a television set, a computer monitor, a flat panel display or other display device. The display device receives data signals from processor 101 through display device controller 122 and displays the information and data signals to the user of computer system 100.

[0026] A video decoder 123 is also coupled to I/O bus 120. Video decoder 123 is a hardware device that translates received encoded data into its original format. According to one embodiment, video decoder 123 is a Moving Picture Expert Group 4 (MPEG-4) decoder. However, one of ordinary skill in the art will appreciate that video decoder 123 may be implemented with other types of MPEG decoders.

[0027] According to one embodiment, computer system 100 supports virtual machines using partitioned memory. In a further embodiment, computer system 100 includes a mechanism to re-map post virtual machine memory to page granular memory. FIG. 2 is a block diagram of one embodiment of processor 101 coupled to chipset 111 and memory device 113. Processor 101 includes partitioning logic 210 and translation lookaside buffer (TLB) 218.

[0028] Partitioning logic 210 supports virtual machine systems by the partitioning of addresses in memory 113. Partitioning logic 210 stores mapping information that indicates the location of pages in memory 113 at TLB 218. In particular, partitioning logic 210 generates a range of addresses for each virtual machine. For example, a 0-1 Gb range may be allocated for a first virtual machine, while 1-2 Gb, and 2-3 Gb ranges are allocated to a second and third virtual machines, respectively.

[0029] TLB 218 is coupled to partitioning logic 210. TLB 218 is a cache of the most frequently used page table entries (PTEs) in memory 113. In particular, TLB 218 includes the current active addresses being used in memory 113. Consequently, it is not necessary to access PTEs in memory 113 each time an address translation is performed.

[0030] In conventional virtual machine systems, partitioning logic 210 and TLB 218 perform all of the necessary address translations. However, it is often desirable to manage memory 113 on an individual page basis, rather than in large regions. With current partitioned memory systems, it is not possible to specify memory with page level flexibility that most operating systems require.

[0031] Chipset 111 includes a TLB 220. TLB 220 is a cache that includes the current active addresses being used at a remap table within memory 113. Memory 113 includes page tables 236 and remap tables 238. Page tables 236 translate the partitioned virtual machine addresses into physical memory addresses. Page tables 236 includes a collection of PTEs. Page tables 236 hold one PTE for each mapped virtual page. To access a page in physical memory, the appropriate PTE is looked up to find where the page resides.

[0032] Similar to page tables 236, remap tables 238 include a list of table entries that specify the remapping of partitioned virtual addresses to page level addresses. In one embodiment, TLB 220 and remap tables 238 are implemented to translate memory addresses back to supporting page level operation, thus, circumventing the range partitioning imposed by processor 101.

[0033]FIG. 5 is a block diagram of another embodiment of processor 101 and a bus master 530 coupled to chipset 111 and memory device 113. Bus master 530 is an I/O device (e.g., disk controller, graphics controller, etc.) that has access to memory 113. An offset register 550 is coupled between bus master 530 and TLB 220.

[0034] Offset register 550 provides mapping to an address space of a virtual machine that controls bus master 530. Typically, the computer system 100 operating system expects that the partitioned virtual machine physical address is the actual address. However, since the address is not the true physical address, because of the chipset remapping, the address used by bus master is not correct. Thus, offset manager 550 and TLB 220 correct the address so that the address is translated the same as the addresses of the operating system running in a VM are. According to one embodiment, TLB 220 may block bus master 530 access to memory 113 based upon a flag bit within TLB 220 base address. This flag can prevent read or write access or both depending on the definition provided by a particular implementation.

[0035]FIG. 3 is a block diagram for one embodiment of a chipset 111. As discussed above, chipset 111 includes TLB 220. TLB 220 includes TLB input 305, TLB output 310, remap directory 320, and remap table 330. TLB input 305 receives a partitioned addresses from partitioning logic 210 within processor 101. TLB output 310 transmits the translated physical address to memory 113.

[0036] Directory entry 320 receives the bottom 10 bits of the partitioned address in order to define a starting location at remap table 330. Remap table 330 receives the next 10 bits that indicate an actual table entry within table 330 that includes the corresponding physical address. After the physical address is selected, the address is transmitted from TLB out 310 along with the first 12 bits of the partitioned address.

[0037]FIG. 4 is a flow diagram of one embodiment of converting a virtual address to a page address. At processing block 410, the processor 101 page tables (e.g., TLB 218) translates a logical address to a virtual memory physical address. At processing block 420, partitioning logic 210 translates the virtual memory physical address to partitioned address space. At processing block 430, the chipset remapping mechanism translates the partitioned address space to the physical address space. At processing block 440, the physical address is transmitted to memory 113.

[0038] The chipset remapping mechanism combines memory partitioning with the advantages of page granular remapping. Thus, the chipset remapping mechanism enables processors that support virtual machines with partitioned memory space to take advantage of the flexibility provided by a page granular memory space. For instance, dynamic resizing of memory for virtual machines, which is nearly impossible in conventional systems, may now be achieved

[0039] Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention. 

What is claimed is:
 1. A computer system comprising: a processor; a chipset, coupled to the processor, to translate partitioned virtual machine memory addresses received from the processor to page level addresses; and a memory device coupled to the chipset.
 2. The computer of claim 1 wherein the chipset comprises a translation lookaside buffer (TLB) that translates the partitioned machine memory addresses to the page level addresses.
 3. The computer of claim 2 wherein the TLB comprises: an input that receives a partitioned address; a remap directory coupled to the input; a remap table coupled to the directory and the input; and an output, coupled to the remap table, that transmits a physical address.
 4. The computer of claim 3 wherein the memory device comprises: remap tables to translate the partitioned virtual machine addresses into physical memory addresses; and page tables to specify the remapping of partitioned virtual machine addresses to page level addresses.
 5. The computer of claim 2 wherein the TLB further comprises: a bus master device; and an offset register coupled to the bus master device and the TLB.
 6. The computer of claim 5 wherein the TLB controls the bus master device permission to access the memory based upon a flag bit within the TLB base address.
 7. The computer of claim 6 wherein the bus master device is a graphics controller.
 8. The computer of claim 6 wherein the bus master device is a disk controller.
 9. A chipset comprising a translation lookaside buffer (TLB) to translate partitioned machine memory addresses received from a processor into page level addresses.
 10. The chipset of claim 9 wherein the TLB comprises: an input that receives a partitioned address; a remap directory coupled to the input; a remap table coupled to the directory and the input; and an output, coupled to the remap table, to transmit a physical address to a memory device.
 11. The chipset of claim 10 wherein the TLB further comprises: a bus master device; and an offset register coupled to the bus master device and the first TLB.
 12. The chipset of claim 11 wherein the TLB controls the bus master device permission to access the memory based upon a flag bit within the TLB base address.
 13. The chipset of claim 11 wherein the bus master device is a graphics controller.
 14. The computer of claim 11 wherein the bus master device is a disk controller.
 15. A method comprising: receiving a partitioned virtual machine memory address at a chipset; and translating the partitioned virtual machine memory addresses received from the processor to page level addresses at the chipset.
 16. The method of claim 15 further comprising: translating a logical address to a virtual machine memory physical address at a processor; and translating the virtual machine memory physical address to a partitioned virtual machine memory address.
 17. The method of claim 16 further comprising transmitting the partitioned virtual machine memory address to the chipset. 